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IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCKTM W
FEATURES:
* * * * * * * * * * * * * * * * *
IDT5V9955
Ref input is 5V tolerant 8 pairs of programmable skew outputs Two separate A and B banks for individual control Low skew: 185ps same pair, 250ps same bank, 350ps both banks Selectable positive or negative edge synchronization on each bank: excellent for DSP applications Synchronous output enable on each bank Input frequency: 2MHz to 200MHz Output frequency: 6MHz to 200MHz 3-level inputs for skew and PLL range control 3-level inputs for feedback divide selection multiply / divide ratios of (1-6, 8, 10, 12) / (2, 4) PLL bypass for DC testing External feedback, internal loop filter 12mA balanced drive outputs Low Jitter: <100ps cycle-to-cycle Power-down mode on each bank Lock indicator on each bank Available in BGA package
DESCRIPTION
The IDT5V9955 is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5V9955 has sixteen programmable skew outputs in eight banks of 2. The two separate PLLs allow the user to independently control A and B banks. Skew is controlled by 3-level input signals that may be hard-wired to appropriate HIGH-MID-LOW levels. The feedback input allows divide-by-functionality from 1 to 12 through the use of the xDS[1:0] inputs. This provides the user with frequency multiplication from 1 to 12 without using divided outputs for feedback. When the xsOE pin is held low, all the xbank outputs are synchronously enabled. However, if xsOE is held high, all the xbank outputs except x2Q0 and x2Q1 are synchronously disabled. The xLOCK is high when the xbank PLL has achieved phase lock. Furthermore, when xPE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When xPE is held low, all the xbank outputs are synchronized with the negative edge of REF. The IDT5V9955 has LVTTL outputs with 12mA balanced drive outputs.
FUNCTIONAL BLOCK DIAGRAM
ALOCK AFS APE REF APD
AsOE
TEST
BPE
BFS
BLOCK
BPD BsOE
3 3 PLL /N 3 3 ADS1:0 A1Q0 A1Q1 Skew Select 3 A1F1:0 3 B1F1:0 3 BDS1:0 3 Skew Select AFB BFB 3 /N 3 3 PLL
3
B1Q0 B1Q1
A2Q0 A2Q1
Skew Select
3 A2F1:0 3 B2F1:0
3 3
Skew Select
B2Q0 B2Q1
A3Q0 A3Q1
3 Skew Select A3F1:0 3 B3F1:0
3 3
Skew Select
B3Q0 B3Q1
A4Q0 A4Q1
Skew Select
3 A4F1:0 3 B4F1:0
3 3
Skew Select
B4Q0 B4Q1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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c 2002 Integrated Device Technology, Inc.
JUNE 2002
DSC 5974/9
IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
6
A3Q1
A4Q0
A4Q1
APE
APD
A4F1
A3F1
AFS
B2F1
B1F1
BDS1
BLOCK
BVDDQ
B1Q0
B1Q1 BGND BGND BGND BGND B4Q0
R
B2Q0 B2Q1 BFB BGND B3Q0 B3Q1
T
5
A3Q0 AGND AFB A2Q1 A2Q0
A
AGND AGND AGND AGND A1Q1
B
AGND AGND AGND AGND A1Q0
C
AGND AVDDQ AVDDQ AVDDQ AVDDQ
D
ASOE AVDDQ AVDDQ ADS0 ALOCK
E
A4F0 AVDDQ AVDDQ A1F0 ADS1
F
A3F0 AVDDQ AVDDQ A2F0 A1F1
G
AVDD AVDDQ REF AGND A2F1
H
BGND TEST BVDDQ BVDD BFS
J
B2F0 BVDDQ BVDDQ B3F0 B3F1
K
B1F0 BVDDQ BVDDQ B4F0 B4F1
L
BDS0 BVDDQ BVDDQ BSOE BPD
M
BVDDQ BVDDQ BVDDQ BGND BPE
N
BGND BGND BGND BGND B4Q1
P
4
3
2
1
FPBGA TOP VIEW
96 BALL FPBGA PACKAGE ATTRIBUTES
1.5mm Max. 1.4mm Nom. 1.3mm Min.
0.8mm
6 5 4 3 2 1 A B C D E F G H J K L M N P R T
TOP VIEW
A 1 2 3
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
5.5mm 4 5 6
13.5mm
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IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDDQ, VDD VI Description Supply Voltage to Ground DC Input Voltage REF Input Voltage Maximum Power Dissipation TSTG TA = 85C TA = 55C Max -0.5 to +4.6 -0.5 to VDD+0.5 -0.5 to +5.5 1.1 1.9 -65 to +150 C Unit V V V W
CAPACITANCE(TA = +25C, f = 1MHz, VIN = 0V)
Parameter CIN Description Input Capacitance REF Others Typ. 8 5 Max. 10 7 Unit pF
NOTE: 1. Capacitance applies to all inputs except TEST, xFS, xnF[1:0], and xDS[1:0].
Storage Temperature Range
NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
PIN DESCRIPTION
Pin Name REF xFB TEST (1) xsOE(1) Type IN IN IN IN Description Reference Clock Input Individual Feedback Inputs for A and B banks When MID or HIGH, disables PLL for A and B banks (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary Table) remain in effect. Set LOW for normal operation. Individual Synchronous Output Enable for A and B banks. When HIGH, it stops clock outputs (except x2Q0 and x2Q1) in a LOW state (for xPE = H) - x2Q0 and x2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0] pins act as output disable controls for individual banks when xnF[1:0] = LL. Set xsOE LOW for normal operation (has internal pull-down). Individual Selectable positive or negative edge control for A and B banks. When LOW/HIGH the outputs are synchronized with the negative/ positive edge of the reference clock (has internal pull-up). xnF[1:0] xFS xnQ[1:0] xDS[1:0] xPD xLOCK VDDQ VDD GND IN IN OUT IN IN OUT PWR PWR PWR 3-level inputs for selecting 1 of 9 skew taps or frequency functions Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.) Individual control on A and B banks. Eight banks of two outputs with programmable skew 3-level inputs for feedback divider selection for A and B banks Power down control. Shuts off either A or B bank of the chip when LOW (has internal pull-up). PLL lock indication signal for A and B banks. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the inputs. Power supply for output buffers Power supply for phase locked loop, lock output, and other internal circuitry Ground
xPE
IN
NOTE: 1. When TEST = MID and xsOE = HIGH, PLL remains active with xnF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless xnF[1:0] = LL.
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IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
PROGRAMMABLE SKEW
Output skew with respect to the REF input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit (tU) which ranges from 625ps to 1.3ns (see Programmable Skew Range and Resolution Table). There are nine skew configurations available for each output pair. These configurations are chosen by the xnF1:0 control pins. In order to minimize the number of control pins, 3-level inputs (HIGH-MIDLOW) are used, they are intended for but not restricted to hard-wiring. Undriven 3-level inputs default to the MID level. Where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. The Control Summary Table shows how to select specific skew taps by using the xnF1:0 control pins.
EXTERNAL FEEDBACK
By providing two separate external feedbacks, the IDT5V9955 gives users flexibility with regard to skew adjustment. The xFB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
xFS = LOW Timing Unit Calculation (tU) VCO Frequency Range (FNOM)(1,2) Skew Adjustment Range(3) Max Adjustment: 7.8125ns 67.5 18.75% Example 1, FNOM = 25MHz Example 2, FNOM = 37.5MHz Example 3, FNOM = 50MHz Example 4, FNOM = 75MHz Example 5, FNOM = 100MHz Example 6, FNOM = 150MHz Example 7, FNOM = 200MHz tU = 1.25ns tU = 0.833ns tU = 0.625ns -- -- -- -- 7.8125ns 135 37.5% -- -- tU = 1.25ns tU = 0.833ns tU = 0.625ns -- -- 7.8125ns 270 75% -- -- -- -- tU = 1.25ns tU = 0.833ns tU = 0.625ns ns Phase Degrees % of Cycle Time 1/(32 x FNOM) 24 to 50MHz xFS = MID 1/(16 x FNOM) 48 to 100MHz xFS = HIGH 1/(8 x FNOM) 96 to 200MHz Comments
NOTES: 1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. 2. The level to be set on xFS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at x1Q1:0, x2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and xFB inputs will be FNOM when the output connected to xFB is undivided and xDS[1:0] = MM. The frequency of the REF and xFB inputs will be FNOM /2 or FNOM /4 when the part is configured for frequency multiplication by using a divided output as the xFB input and setting xDS[1:0] = MM. Using the xDS[1:0] inputs allows a different method for frequency multiplication (see Divide Selection Table). 3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed xQ output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed -4tU in addition to whatever skew value is programmed for those outputs. `Max adjustment' range applies to output pairs 3 and 4 where 6tU skew adjustment is possible and at the lowest FNOM value.
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IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
DIVIDE SELECTION TABLE
xDS [1:0] LL LM LH ML MM MH HL HM HH xFB Divide-by-n 2 3 4 5 1 6 8 10 12 Permitted Output Divide-by-n connected to xFB(1) 1 or 2 1 1, 2, or 4 1 or 2 1, 2, or 4 1 or 2 1 or 2 1 1
NOTE: 1. Permissible output division ratios connected to xFB. The frequency of the REF input will be FNOM/N when the part is configured for frequency multiplication by using an undivided output for xFB and setting xDS[1:0] to N (N = 1-6, 8, 10, 12).
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0 LL (1) LM LH ML MM MH HL HM HH Skew (Pair #1, #2) -4tU -3tU -2tU -1tU Zero Skew 1tU 2tU 3tU 4tU Skew (Pair #3) Divide by 2 -6tU -4tU -2tU Zero Skew 2tU 4tU 6tU Divide by 4 Skew (Pair #4) Divide by 2 -6tU -4tU -2tU Zero Skew 2tU 4tU 6tU Inverted (2)
NOTES: 1. LL disables outputs if TEST = MID and xsOE = HIGH. 2. When pair #4 is set to HH (inverted), xsOE disables pair #4 HIGH when xPE = HIGH, xsOE disables pair #4 LOW when xPE = LOW.
RECOMMENDED OPERATING RANGE
Symbol VDD/VDDQ TA Description Power Supply Voltage Ambient Operating Temperature Min. 3 -40 Typ. 3.3 +25 Max. 3.6 +85 Unit V C
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IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol VIH VIL VIHH VIMM VILL IIN Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Voltage(2) Input MID Voltage
(2) (2)
Conditions(1) Guaranteed Logic HIGH (REF, xFB Inputs Only) Guaranteed Logic LOW (REF, xFB Inputs Only) 3-Level Inputs Only 3-Level Inputs Only 3-Level Inputs Only VIN = VDD or GND VDD = Max. VIN = VDD HIGH Level MID Level LOW Level
Min. 2 -- VDD-0.6 VDD/2-0.3 --
Max. -- 0.8 -- VDD/2+0.3 0.6 +5 +400 +100 -- -- +100 -- -- 0.4 0.4
Unit V V V V V A
Input LOW Voltage
Input Leakage Current (REF, xFB Inputs Only)
-5
--
I3 IPU IPD VOH VOL
3-Level Input DC Current (TEST, xFS, xnF[1:0], xDS[1:0]) Input Pull-Up Current (xPE, xPD) Input Pull-Down Current (xsOE) Output HIGH Voltage Output LOW Voltage
VIN = VDD/2 VIN = GND VDD = Max., VIN = GND VDD = Max., VIN = VDD
-100 -400 -25
-- 2.4 2.4 -- --
A A A V V
VDD = Min., IOH = -2mA (xLOCK Output) VDD = Min., IOL = 2mA (xLOCK Output)
VDDQ = Min., IOH = -12mA (xnQ[1:0] Outputs) VDDQ = Min., IOL = 12mA (xnQ[1:0] Outputs)
NOTES: 1. All conditions apply to A and B banks. 2. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
POWER SUPPLY CHARACTERISTICS
Symbol IDDQ Parameter Quiescent Power Supply Current Test Conditions(1) VDD = Max., TEST = MID, REF = LOW, xPE = LOW, xsOE = LOW, xPD = HIGH xFS = MID, All outputs unloaded IDDPD Power Down Current VDD = Max., PD = LOW, xsOE = LOW xPE = HIGH, TEST = HIGH, xFS = HIGH xnF[1:0] = HH, xDS[1:0] = HH IDD Power Supply Current per Input HIGH (REF and xFB inputs only) xFS = L IDDD Dynamic Power Supply Current per Output xFS = M xFS = H xFS = L, FVCO = 50MHz, CL = 0pF ITOT Total Power Supply Current xFS = M, FVCO = 100MHz, CL = 0pF xFS = H, FVCO = 200MHz, CL = 0pF
NOTES: 1. Measurements are for divide-by-1 outputs, xnF[1:0] = MM, and xDS[1:0] = MM. All conditions apply to A and B banks. 2. For nominal voltage and temperature.
Typ.(2) 40
Max. 60
Unit mA
--
50
A
VIN = 3V, VDD = Max., xPD = LOW, TEST = HIGH
1 190 150 130 112 160 250
60 290 230 200 -- -- --
A
A/MHz
mA
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IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
INPUT TIMING REQUIREMENTS
Symbol tR, tF tPWC DH FREF Description(1) Maximum input rise and fall times, 0.8V to 2V Input clock pulse, HIGH or LOW Input duty cycle xFS = LOW Reference clock input frequency xFS = MID xFS = HIGH
NOTE: 1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
Min. -- 2 10 2 4 8
Max. 10 -- 90 50 100 200
Unit ns/V ns % MHz
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IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol FNOM tRPWH tRPWL tU tSKEWPR tSKEWB tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tDEV t()1-3 t()H t()M t()L1-6 t()L8-12 tODCV tPWH tPWL tORISE tOFALL tLOCK tCCJH tCCJHA tCCJM tCCJL tCCJLA Parameter VCO Frequency Range REF Pulse Width HIGH(1) REF Pulse Width LOW
(1)
Min. 2 2 -- --
(5)
Typ. -- -- See Control Summary Table 50 0.1 0.1 0.1 0.2 0.15 0.3 -- -- -- -- -- -- 0 -- -- 0.7 0.7 -- -- -- -- -- --
Max. -- -- 185 0.35 0.25 0.25 0.5 0.5 0.9 0.75 0.25 0.25 0.5 0.7 1 1 1.5 2 1.5 1.5 0.5 100 150 150 200 300
Unit ns ns ps ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
See Programmable Skew Range and Resolution Table
Programmable Skew Time Unit Zero Output Matched-Pair Skew (xnQ0, xnQ1)(2,3) Bank Skew(4) Zero Output Skew (All Outputs from the same A or B bank) Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)
(6)
-- -- -- -- -- --
(8)
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)(6) Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)(6) Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)(2) Device-to-Device Skew(2,7) Static Phase Offset (xFS = L, M, H) (FB Divide-by-n = 1, 2, 3) Static Phase Offset (xFS = H)(8) Static Phase Offset (xFS = M)
(8)
Static Phase Offset (xFS = L) (xFB Divide-by-n = 1, 2, 3, 4, 5, 6)(8) Static Phase Offset (xFS = L) (xFB Divide-by-n = 8, 10, 12) Output Duty Cycle Variation from 50% Output HIGH Time Deviation from 50%(9) Output LOW Time Deviation from 50% Output Rise Time Output Fall Time PLL Lock Time
(11,12) (10) (8)
-0.25 -0.25 -0.5 -0.7 -1 -1
-- -- 0.15 0.15 -- -- -- -- -- --
Cycle-to-Cycle Output Jitter (peak-to-peak) (divide by 1 output frequency, xFS = H, FB divide-by-n=1,2) Cycle-to-Cycle Output Jitter (peak-to-peak) (divide by 1 output frequency, xFS = H, FB divide-by-n=any) Cycle-to-Cycle Output Jitter (peak-to-peak) (divide by 1 output frequency, xFS = M) Cycle-to-Cycle Output Jitter (peak-to-peak) (divide by 1 output frequency, xFS = L, FREF > 3MHz) Cycle-to-Cycle Output Jitter (peak-to-peak) (divide by 1 output frequency, xFS = L, FREF < 3MHz)
ps
NOTES: 1. Refer to Input Timing Requirements table for more detail. 2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load. 3. tSKEWPR is the skew between a pair of outputs (xnQ0 and xnQ1) when all sixteen outputs are selected for 0tU. 4. tSKEWB is the skew between outputs (xnQ0 and xnQ1) from A and B banks when they are selected for 0tU. 5. tSK(0) is the skew between outputs when they are selected for 0tU. 6. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (x4Q0 and x4Q1 only with x4F0 = x4F1 = HIGH), and Divided (x3Q1:0 and x4Q1:0 only in Divideby-2 or Divide-by-4 mode). Test condition: xnF0:1=MM is set on unused outputs. 7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.) 8. t is measured with REF input rise and fall times (from 0.8V to 2V) of 0.5ns. Measured from 1.5V on REF to 1.5V on xFB. 8. Measured at 2V. 10. Measured at 0.8V. 11. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or xFB until tPD is within specified limits. 12. Lock detector may be unreliable for input frequencies less than approximately 4MHz, or for input signals which contain significant jitter.
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IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
AC TEST LOADS AND WAVEFORMS
VDDQ
150 Output Output
20pF
150
20pF
For LOCK output
For all other outputs
tORISE
2.0V
tOFALL tPWH
VTH = 1.5V
0.8V
tPWL
LVTTL Output Waveform
1ns 3.0V 2.0V VTH = 1.5V 0.8V 0V
1ns
LVTTL Input Test Waveform
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IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
AC TIMING DIAGRAM
tREF tRPWH
REF
tRPWL
t()
FB
tODCV
tODCV
tCCJH, HA,
M, L, LA Q
tSKEWPR,B tSKEW0, 1
OTHER Q
tSKEWPR,B tSKEW0, 1
tSKEW2
INVERTED Q
tSKEW2
tSKEW3, 4 tSKEW3, 4
REF DIVIDED BY 2
tSKEW3, 4
tSKEW1, 3, 4
tSKEW2, 4
REF DIVIDED BY 4
NOTES: PE: Skew: tSKEWPR: tSKEWB: tSKEW0: tDEV: tODCV:
The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align. The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with 75 to VDDQ/2. The skew between a pair of outputs (xnQ0 and xnQ1) when all eight outputs are selected for 0tU. The skew between outputs (xnQ0 and xnQ1) from A and B banks when they are selected for 0tU. The skew between outputs when they are selected for 0tU. The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.) The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tPWH is measured at 2V. tPWL is measured at 0.8V. tORISE and tOFALL are measured between 0.8V and 2V. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
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IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Package
I BF
-40C to +85C (Industrial) Fine Pitch Ball Grid Array
5V9955
3.3V Programmable Skew Dual PLL Clock Driver TurboClock W
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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